Register spilling is an expensive operation in that it is comparatively slow in an environment where operational speed is the primary goal in the design of computer architectures, and in software intended to take full advantage of such architectures. In general, register spilling involves the movement of register contents from the CPU's register file to a much slower and less efficiently accessed secondary storage medium. Register spilling occurs when, because all available registers are in use, it is necessary to insert instructions in generated code to store the content of a register into a memory location. This is done in order to free up the register for allocation to a computation. Because of the inherent cost of register spilling, much effort has been directed toward the allocation and usage of registers, with one of the principle goals of such effort being the minimization of the necessity to spill registers. An example of such an effort is found in U.S. Pat. No. 5,418,958, entitled Register Allocation by Decomposing, Re-Connecting and Coloring Hierarchical Program Regions, issued to the present inventor.
SPARC-V9 is a microprocessor specification created by the SPARC Architecture Committee of SPARC International. SPARC-V9 is not a specific chip. Rather, it is an architectural specification that can be implemented as a microprocessor by anyone securing a license from SPARC International. FIG. 1 depicts an aspect of the SPARC architecture in diagrammatic form. A computer 10 has therein a microprocessor 12. One skilled in the art will recognize that the microprocessor 12 is greatly out of proportion in the diagrammatic view of FIG. 1, and only a few relevant logical components of the microprocessor 12 are illustrated therein, in order to better illustrate the aspects of the computer 10 which are relevant to this present disclosure. The computer 10 will generally be equipped with a number of ordinary peripheral devices, such as a monitor, a keyboard, and the like, and such peripheral devices will include an external memory device 13 for transferring programs and data into and out of the computer 10. The external memory device 13 can be any of a great number of different device types, such as a floppy disk drive, a hard disk drive, a CD ROM drive, or the like. Also, it should be noted that, although the microprocessor 12 is illustrated in the view of FIG. 1 as an integral unit, it is not required by the SPARC-V9 specification that the SPARC-V9 architecture be implemented in a single chip.
The V9 version of the SPARC architecture defines thirty two (32) single precision (32 bit) floating point registers 14 which are designated as %f0 through %f31 inclusive, and thirty two (32) double precision (64 bit) floating point registers 16 designated as %d0 through %d62 inclusive. The first sixteen (16) double precision registers 16 overlap with the thirty two (32) single precision registers 14 such that each double precision register 16 corresponds to and uses the same physical or logical memory as two of the single precision registers 14. For example, the double precision floating point register 16 designated %d0 overlaps with the two single precision registers 14 which are designated as %f0 and %f1. The second sixteen (16) double precision registers 16 do not overlap with the single precision registers 14. The first sixteen (16) double precision registers 16 are designated by even address numbers %d0, %d2, %d4 . . . %d30, while the second sixteen (16) double precision registers 16 are designated herein by even address numbers %d32, %d34, %d36 . . . %d62. This arrangement is discussed in more detail in The SPARC Architecture Manual edited by David L. Weaver and Tom Germond and published by PTR Prentice Hall under the auspices Of SPARC INTERNATIONAL (ISBN#0-13-099227-5). It should be noted that the terms "single precision" and "double precision" are sometimes susceptible to different definitions. As used herein, these terms will be synonymous with "low precision" and "high precision", whether low and high precision are defined as being single and double precision, respectively, or double and quad precision respectively, or the like.
A stack memory 18 is also included in the computer 10, as depicted in the logical diagrammatic view of FIG. 1. As used herein, the term "stack memory" is intended to refer to that portion of a memory unit which is allocated as a "run time memory". An example of a typical register spill to and reload from the stack memory 18 might be annotated as follows:
spill: PA1 reload:
st %f2,%sp+92! PA2 Id %sp+92!, %f10
where;
`st` and `Id` are the spill and reload commands, respectively;
%sp is stack pointer location--in this example, the %sp+92 indicates a stack memory location of %sp+92--this memory location is an example only and is of no articular significance;
%f# (where "#" represents an integer) defines a single precision floating point register 14 having a size of 4 bytes such that, in the example above, the single precision floating point register %f2 is depicted as being first spilled into the memory stack 18 at location sp+92, and then the data in location sp+p2 is reloaded into the single precision floating point register %f10.
According to the SPARC-V9 architecture, single precision arithmetic operations may only be applied to operand within the single precision registers 14. Furthermore, the result of single precision arithmetic operations may only write to the single precision registers 14. Therefore, when only single precision arithmetic operations are being accomplished, or during a combination of single precision and double precision arithmetic operations which is weighted toward the single precision operations, the double precision registers 16 will be underutilized, while the available quantity of single precision registers 14 may be insufficient to prevent the necessity for excessive register spilling.
To the inventor's knowledge, no prior art method or means exist for allowing the use of the double precision registers 16 to augment the simple precision registers 14. Indeed, since the SPARC-V9 specification specifically disallows the writing of single precision data to the double precision registers 16, it would seem to run counter to both intuition and the intent of the SPARC-V9 creators to accomplish this.